mm74hc4020 mm74hc4040 14-stage binary counter 12-stage binary counter general description the mm54hc4020/mm74hc4020, mm54hc4040/ mm74hc4040, are high speed binary ripple carry counters. these counters are implemented utilizing advanced silicon-gate cmos technology to achieve speed perfor- mance similar to ls-ttl logic while retaining the low power and high noise immunity of cmos. the 'hc4020 is a 14 stage counter and the 'hc4040 is a 12-stage counter. both devices are incremented on the fall- ing edge (negative transition) of the input clock, and all their outputs are reset to a low level by applying a logical high on their reset input. these devices are pin equivalent to the cd4020 and cd4040 respectively. all inputs are protected from damage due to static discharge by protection diodes to v cc and ground. features n typical propagation delay: 16 ns n wide operating voltage range: 26v n low input current: 1 a maximum n low quiescent current: 80 a maximum (74hc series) n output drive capability: 10 ls-ttl loads connection diagrams dual-in-line packages 'hc4020 ds005216-1 'hc4040 ds005216-3 order number mm54hc4020/4040 or mm74hc4020/4040 april 1998 mm74hc4020 mm74hc4040 14-stage binary counter 12-stage binary counter ? 1998 fairchild semiconductor corporation ds005216 www.fairchildsemi.com
absolute maximum ratings (notes 2, 1) supply voltage (v cc ) ?0.5 to +7.0v dc input voltage (v in ) ?1.5 to v cc +1.5v dc output voltage (v out ) ?0.5 to v cc +0.5v clamp diode current (i cd ) 20 ma dc output current, per pin (i out ) 25 ma dc v cc or gnd current, per pin (i cc ) 50 ma storage temperature range (t stg ) ?65c to +150c power dissipation (p d ) (note 3) 600 mw s.o. package only 500 mw lead temperature (t l ) (soldering 10 seconds) 260c operating conditions min max units supply voltage (v cc )26v dc input or output voltage 0 v cc v (v in ,v out ) operating temp. range (t a ) mm74hc ?40 +85 c mm54hc ?55 +125 c input rise or fall times (t r ,t f )v cc = 2.0v 1000 ns v cc = 4.5v 500 ns v cc = 6.0v 400 ns dc electrical characteristics (note 4) t a = 25c 74hc 54hc symbol parameter conditions v cc t a = ?40 to 85c t a = ?55 to 125c units typ guaranteed limits v ih minimum high level input 2.0v 1.5 1.5 1.5 v voltage 4.5v 3.15 3.15 3.15 v 6.0v 4.2 4.2 4.2 v v il maximum low level input 2.0v 0.5 0.5 0.5 v voltage (note 5) 4.5v 1.35 1.35 1.35 v 6.0v 1.8 1.8 1.8 v v oh minimum high level output v in = v ih or v il voltage |i out | 20 a 2.0v 2.0 1.9 1.9 1.9 v 4.5v 4.5 4.4 4.4 4.4 v 6.0v 6.0 5.9 5.9 5.9 v v in = v ih or v il |i out | 4.0 ma 4.5v 4.2 3.98 3.84 3.7 v |i out | 5.2 ma 6.0v 5.7 5.48 5.34 5.2 v v ol maximum low level output v in = v ih or v il voltage |i out | 20 a 2.0v 0 0.1 0.1 0.1 v 4.5v 0 0.1 0.1 0.1 v 6.0v 0 0.1 0.1 0.1 v v in = v ih or v il |i out | 4.0 ma 4.5v 0.2 .26 0.33 0.4 v |i out | 5.2 ma 6.0v 0.2 .26 0.33 0.4 v i in maximum input current v in = v cc or gnd 6.0v 0.1 1.0 1.0 a i cc maximum quiescent supply v in = v cc or gnd 6.0v 8.0 80 160 a current i out = 0a note 1: maximum ratings are those values beyond which damage to the device may occur. note 2: unless otherwise specified all voltages are referenced to ground. note 3: power dissipation temperature derating e plastic ano package: ?12 mw/c from 65c to 85c; ceramic ajo package: ?12 mw/c from 100c to 125c. note 4: for a power supply of 5v 10 % the worst case output voltages (v oh , and v ol ) occur for hc at 4.5v. thus the 4.5v values should be used when designing with this supply. worst case v ih and v il occur at v cc = 5.5v and 4.5v respectively. (the v ih value at 5.5v is 3.85v.) the worst case leakage current (i in ,i cc , and i oz ) occur for cmos at the higher voltage and so the 6.0v values should be used. note 5: v il limits are currently tested at 20 % of v cc . the above v il specification (30 % of v cc ) will be implemented no later than q1, cy'89. www.fairchildsemi.com 2
ac electrical characteristics v cc = 5v, t a = 25c, c l = 15 pf, t r = t f = 6ns symbol parameter conditions typ guaranteed units limit f max maximum operating frequency 50 30 mhz t phl ,t plh maximum propagation (note 6) 17 35 ns delay clock to q t phl maximum propagation 16 40 ns delay reset to any q t rem minimum reset 10 20 ns removal time t w minimum pulse width 10 16 ns ac electrical characteristics v cc = 2.0v to 6.0v, c l = 50 pf, t r = t f = 6 ns (unless otherwise specified) t a = 25c 74hc 54hc symbol parameter conditions v cc t a = ?40 to 85c t a = ?55 to 125c units typ guaranteed limits f max maximum operating 2.0v 10 6 5 4 mhz frequency 4.5v 40 30 24 20 mhz 6.0v 50 35 28 24 mhz t phl ,t plh maximum propagation 2.0v 80 210 265 313 ns delay clock to q 1 4.5v 21 42 53 63 ns 6.0v 18 36 45 53 ns t phl, t plh maximum propagation 2.0v 80 125 156 188 ns delay between stages 4.5v 18 25 31 38 ns from q n to q n+1 6.0v 15 21 26 31 ns t phl maximum propagation 2.0v 72 240 302 358 ns delay reset to any q 4.5v 24 48 60 72 ns ('4020 and '4040) 6.0v 20 41 51 61 ns t rem minimum reset 2.0v 100 126 149 ns removal time 4.5v 20 25 50 ns 6.0v 16 21 25 ns t w minimum pulse width 2.0v 90 100 120 ns 4.5v 16 20 24 ns 6.0v 14 18 20 ns t tlh ,t thl maximum 2.0v 30 75 95 110 ns output rise 4.5v 10 15 19 22 ns and fall time 6.0v 9 13 16 19 ns t r ,t f maximum input rise and 1000 1000 1000 ns fall time 500 500 500 ns 400 400 400 ns c pd power dissipation (per package) 55 pf capacitance (note 7) c in maximum input 5 10 10 10 pf capacitance note 6: typical propagation delay time to any output can be calculated using: t p = 17+12(n1) ns; where n is the number of the output, q w ,atv cc = 5v. note 7: c pd determines the no load dynamic power consumption, p d = c pd v cc 2 f+i cc v cc , and the no load dynamic current consumption, i s = c pd v cc f+i cc . 3 www.fairchildsemi.com
logic diagrams mm54hc4020/mm74hc4020 ds005216-5 mm54hc4040/mm74hc4040 ds005216-7 www.fairchildsemi.com 4
timing diagram ds005216-11 5 www.fairchildsemi.com
physical dimensions inches (millimeters) unless otherwise noted order number mm54hc4020j, mm54hc4024j, MM54HC4040J, mm74hc4020j, mm74hc4024j, or mm74hc4040j package j14a order number mm54hc4020j, mm54hc4024j, MM54HC4040J, mm74hc4020j, mm74hc4024j, or mm74hc4040j package j16a www.fairchildsemi.com 6
physical dimensions inches (millimeters) unless otherwise noted (continued) order number mm74hc4020n, mm74hc4024n or mm74hc4040n package n14a order number mm74hc4020n, mm74hc4024n or mm74hc4040n package n16e 7 www.fairchildsemi.com
life support policy fairchild's products are not authorized for use as critical components in life support de- vices or systems without the express written approval of the president of fairchild semi- conductor corporation. as used herein: 1. life support devices or systems are devices or sys- tems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor corporation americas customer response center tel: 1-888-522-5372 www.fairchildsemi.com fairchild semiconductor europe fax: +49 (0) 1 80-530 85 86 email: europe.support@nsc.com deutsch tel: +49 (0) 8 141-35-0 english tel: +44 (0) 1 793-85-68-56 italy tel: +39 (0) 2 57 5631 fairchild semiconductor hong kong ltd. 13th floor, straight block, ocean centre, 5 canton rd. tsimshatsui, kowloon hong kong tel: +852 2737-7200 fax: +852 2314-0061 national semiconductor japan ltd. tel: 81-3-5620-6175 fax: 81-3-5620-6179 mm74hc4020 mm74hc4040 14-stage binary counter 12-stage binary counter fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications.
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